riscv

CHERI: putting the bounds in the pointer

20 October 2026 · cheri hardware memory-safety riscv

The hardware answer to the problem eBPF and WASM solve in software: a pointer that carries its own bounds and permissions, enforced in silicon. Still an unratified RISC-V extension, whatever the coverage implies.

RISC-V: an ISA you are allowed to read

22 July 2026 · riscv hardware open-source architecture

The Server SoC, Boot and Server Platform specifications are ratified. What makes it interesting is the specification being nobody's property, rather than the instruction set itself.